From geometry to the watt
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PRM-WP-2026-014
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v1.0 · Technical draft
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R&D · Energy · Data Center · e-Mobility
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Internal / Partners under NDA
0 — Executive summary
The constraint that shifts the frontier toward power
At ISCAS 2026 in Shanghai, Huawei proposed replacing the geometric scaling of Moore’s Law with temporal scaling: optimizing the time a signal takes to propagate through the chip (the τ constant) instead of transistor size. Its LogicFolding architecture aims to gain density and performance through 3D integration and shorter critical paths, on mature nodes that China can actually manufacture.
For Premium, what matters is not the dispute over whether τ deserves to be called a “law”. It is the inevitable physical consequence of any path that stacks more logic into less volume — whether from Huawei, TSMC, Apple or NVIDIA: power density rises, heat concentrates, and the performance ceiling is no longer set by the transistor but by the ability to deliver clean energy to the die and extract the resulting heat.
This document traces that causal chain across four derivatives — energy consumption, performance, heat extraction and voltage architecture — and places Premium’s opportunity at the center of the last three.
1 — The paradigm shift
What Huawei proposed, and what is real about it
On May 25, 2026, He Tingbo — president of Huawei’s semiconductor business — presented the Tau (τ) Scaling Law and two supporting technologies: LogicFolding, which folds 2D circuits into vertical 3D stacks to shorten critical-path wiring, and UnifiedBus, a protocol to reduce communication latency at system level.
The core idea is sound and not new in itself: below ~10 nm, interconnect delay (the RC constant of the wiring) dominates over gate delay. The entire industry is already moving toward system scaling — backside power delivery, 3D stacking, hybrid bonding, the CFET roadmap. What Huawei does is turn that axis into corporate doctrine, because sanctions (no EUV lithography from ASML since 2023) close off the geometric axis.
Critical reading: “1.4 nm-equivalent density” is not being at 1.4 nm. It is functional density through stacking, and stacking shifts the problem — it does not eliminate it — toward three fronts that are precisely the domain of power electronics and thermal engineering:
- Volumetric power density: more active logic in fewer mm³.
- Current delivery: feeding the inner layers of a 3D stack without the power distribution network (PDN) “choking” them.
- Heat dissipation: extracting heat from the interior of a solid, not just from a surface.
In other words: Huawei’s path, just like its rivals’, increases the strategic value of advanced power conversion and cooling. The rest of this document explains why.
2 — Derivative I · Energy consumption
Two layers of energy: the one that computes and the one lost along the way
The energy consumption of a computing system splits into two layers with very different dynamics:
Compute layer (on the die)
Dynamic energy follows approximately P ≈ α·C·V²·f. Reducing τ and wiring length lowers the effective capacitance C and allows, for the same frequency, operation at a lower voltage V — and the dependence on V is quadratic. This is where LogicFolding’s claimed +40% efficiency lives. It is a real gain, but confined to the chip.
Distribution and cooling layer (off the die)
At rack and data-center scale, a growing fraction of the energy never gets to compute: it is lost in voltage conversions, in distribution (I²R losses) and in moving heat (cooling overhead, reflected in PUE). As AI accelerators scale from hundreds of watts to several kilowatts per package, this second layer dominates total cost of ownership.
3 — Derivative II · Performance
The performance ceiling is, increasingly, a power ceiling
Temporal scaling explicitly acknowledges that modern performance — and AI performance in particular — is limited by data movement, not transistor count. UnifiedBus and LogicFolding attack that “memory wall”. But there is a second wall, physical and less discussed:
- A chip can only switch as fast as it can be fed. Increasingly aggressive current transients (di/dt) demand a very-low-impedance PDN and point-of-load (PoL) regulators millimeters from the silicon.
- A chip can only sustain its frequency as long as it can be cooled. Thermal throttling is the most direct way a cooling shortfall turns into lost performance.
Thus, the +12.7% frequency that LogicFolding promises only materializes in the field if power delivery and thermals keep up. Delivered performance is the minimum between what the silicon can do and what the power infrastructure allows it to do.
4 — Derivative III · Heat extraction
From a surface problem to a volume problem
3D stacking changes the nature of the thermal problem. A planar chip dissipates power per unit of surface (W/cm²); a 3D stack concentrates it per unit of volume (W/cm³), and the inner layers sit far from any heat-exchange surface. The progression of solutions is well known:
| Thermal stage | Indicative capacity | Power implication |
|---|---|---|
| Forced air | up to ~0.5–1 kW/package | Sufficient for classic SoCs; exhausted for AI. |
| Direct-to-chip liquid (D2C) | ~1–3 kW/package | Emerging standard in AI racks. |
| Immersion / advanced cold plate | several kW | Rack density >100 kW. |
| Embedded microfluidics (in-stack) | experimental | Cooling the inner layers of the 3D stack. |
5 — Derivative IV · Voltage architecture
Bringing high voltage close to the chip: the quadratic lever
Here lies the core of Premium’s argument. Delivered power is P = V · I. For a given power, raising the voltage V proportionally reduces the current I. And since conduction loss is Ploss = I² · R, that loss falls with the square of the current reduction. It is the difference between a linear improvement and a quadratic one.
Relative conduction loss (same power, same conductor)
100%
6.25%
0.09%
0.02%
The delivery chain and the industry’s direction
The design consequence is twofold: raise the distribution voltage and bring the final conversion closer to the load, minimizing the high-current run. The industry is already on this path:
Power delivery spine: voltage steps down and current steps up toward the die
HVDC ~400–800 V
↑ current
48 V
↑↑
12 V → core
↑↑↑
<1 V
hundreds of A
Goal: keep high voltage for as long a run as possible and convert to low voltage / high current only in the last millimeter.
- Rack/row level → HVDC. The industry is migrating to DC distribution in the 400–800 V class to feed AI racks from hundreds of kW to megawatts, reducing copper, losses and the number of conversions.
- Bus level → 48 V. The de facto standard of the modern data center (including the 48 V busbar of OCP’s Open Rack) versus legacy 12 V: same power, 1/4 of the current, ~1/16 of the loss.
- Package level → PoL and vertical delivery. Final conversion from 48 V to core voltage (<1 V) integrated under or next to the die, and even backside power delivery, so that the very high current travels minimal distances.
Wide-bandgap (GaN and SiC) is the enabler: it allows faster, denser and more efficient converters that make this near-load conversion viable. It is exactly the terrain where Premium adds value.
6 — Infrastructure and cost
Why voltage is also a capex and opex decision
Raising the distribution voltage does not just save energy: it makes the infrastructure cheaper. The chain of effects is direct:
| Lever | Effect on consumption (opex) | Effect on infrastructure (capex) |
|---|---|---|
| ↑ Distribution voltage | I²R loss falls with the square of the current. | Thinner, cheaper conductors and busbars; less copper. |
| ↓ Conversion stages | Every conversion avoided removes its loss. | Fewer conversion units, less space, fewer points of failure. |
| Conversion close to the load | The high-current run is shortened to the minimum. | Simpler PDN on the board; better use of the rack. |
| Fewer losses → less heat | Cooling overhead drops (better PUE). | Lower installed cooling capacity per useful kW. |
The result is a virtuous circle: fewer losses mean less heat, which means less cooling, which means less energy and less infrastructure for the same useful power delivered to the silicon. In the era of temporal scaling — where silicon densifies without getting cheaper per node — system-level savings shift decisively to the power architecture.
7 — Premium’s positioning
Where Premium fits in this scenario
Huawei’s move illustrates a truth that applies to the whole industry, not just China: as performance densifies in volume, the advantage shifts to whoever can power and cool that volume. Premium operates precisely in that layer, and with criteria — minimum cost, open hardware/software, no vendor lock-in, performance — that fit a market looking for alternatives to both technical and geopolitical lock-in.
Lines of opportunity:
- High-voltage to point-of-load conversion with wide-bandgap (GaN/SiC) for data center and AI: rack HVDC → 48 V → core, with the final conversion as close as possible to the die.
- Power architectures for high-density racks aligned with OCP (48 V busbar, evolution toward HVDC), leveraging the open-hardware mandate against closed solutions.
- Power–thermal co-design: modules where energy delivery and heat extraction are designed together, not separately — the true technical differentiator of the 3D era.
- Vendor independence at system scale: a neutral power and thermal layer works equally under Western silicon (TSMC/Apple/NVIDIA) or the Chinese path (Huawei/Ascend), covering the ecosystem’s bifurcation.
The useful paradox: sanctions pushed Huawei down a path that increases the world’s dependence on good power delivery and cooling. That demand is agnostic as to who makes the chip — and that is precisely the neutral, open space where Premium can compete.
8 — Conclusion
The lithographer hands the baton to the power engineer
The Tau Law is neither a new law of physics nor the end of Moore; it is constraint-driven innovation. But its value for Premium is independent of whether it succeeds as a standard: any path that stacks more compute into less volume — from East or West — concentrates power and heat, and moves the performance and cost limit to the energy delivery and heat dissipation layer.
Keeping high voltage for as long a run as possible, converting close to the load with wide-bandgap technology, and co-designing power and thermals as a single problem is engineering’s answer to the era of temporal scaling. The verdict on Huawei will come with the Kirin teardowns this autumn; Premium’s is decided by how it capitalizes on a frontier that is shifting, unmistakably, into its domain.
§ Sources
- Huawei, official press release: “HUAWEI Presents the Tau (τ) Scaling Law” (ISCAS 2026, Shanghai, May 25, 2026).
- CGTN: “From geometry to time: Decoding Huawei’s Tau (τ) Scaling Law” and note on the 1.4 nm-equivalent density target for 2031.
- 36Kr (analysis): balanced assessment of the Tau Law and the redefinition of “mature process” as “high-performance process”.
- TechWire Asia: Ascend / DeepSeek V4 context and demand for domestic AI silicon.
- Canal TI: “Huawei busca reescribir las reglas de los procesadores” (June 8, 2026) — source article.
- Power engineering fundamentals (P = V·I; I²R loss; P ≈ α·C·V²·f) and distribution architecture trends (OCP Open Rack 48 V; industry migration to 400–800 V-class HVDC) — domain technical knowledge.
The LogicFolding figures (+53.5% density, +40% efficiency, +12.7% frequency, 1.4 nm-equivalent target by 2031) are Huawei’s claims pending independent validation. The voltage-loss illustrations are normalized calculations for explanatory purposes, not product specifications.
