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White paper GaN in a 1/16th brick NP-0847

White paper – GaN in a 1/16th Brick: 300 W DC/DC Conversion with Natural Convection

White Paper · GaN & Thermal Design

GaN in a 1/16th Brick: 300 W Non-Isolated DC/DC Conversion with Natural Convection

How gallium-nitride switching and CFD-driven heatsink design remove the fan from a standard-footprint point-of-load converter — for power, hardware and thermal design engineers

Premium PSUPowering Your Challenge
300 W
Continuous output · 405 W peak for 60 s
98 %
Peak efficiency
−17 %
Heatsink thermal resistance · 13.6 → 11.3 K/W
−40 %
Heatsink aluminium mass · 24 g → 15 g

Executive summary

Designers of 24 V and 48 V industrial systems are asked to deliver more power to their point-of-load rails while removing fans and keeping the board area they already have. The NP-0847 is Premium PSU’s answer to that request: a non-isolated synchronous buck converter in the industry-standard 1/16th-brick footprint (33.0 × 22.9 mm) that converts 9 V to 54 V into an adjustable 3.3 V to 15 V output, delivering up to 20 A and 300 W (405 W peak for 60 s) with efficiency of up to 98 % and natural-convection cooling [1].

Two design decisions make this possible:

  • Gallium-nitride (GaN) power switches. Enhancement-mode GaN HEMTs have no reverse-recovery charge and much lower gate and output charge than silicon MOSFETs [4], so each switching edge wastes less energy. A GaN-optimised controller with smart near-zero dead-time control keeps the remaining transition losses to a minimum.
  • A heatsink designed by simulation. A 3D conjugate CFD study of 40 candidate geometries replaced a commercial straight-fin profile with a 48-pin array. Heatsink-to-ambient thermal resistance fell by 17 % (13.6 K/W to 11.3 K/W) while aluminium mass fell by 40 % (24 g to 15 g), in the same footprint and height [3].

This paper explains the technology behind the module, its architecture and thermal design, and gives the information an engineer needs to design it in.

Download the full white paper (PDF)

Includes the complete specification tables, pinout, hole pattern, trim table and the recommended application circuit for the NP-0847.

Download PDF

1. The design challenge

1.1 Power density without forced air

Point-of-load converters fed from a 24 V or 48 V bus are common in industrial automation, communications and transport equipment. Fan-cooled designs reach high power density, but a fan adds acoustic noise, a filter to maintain and a wear-out component that often sets the service interval of the whole system. Removing it moves the entire thermal budget onto conduction and natural convection, which only works if the converter dissipates very little and the heat path to ambient is short.

1.2 Where silicon reaches its limits

In a hard-switched synchronous buck converter, silicon MOSFETs lose energy at every edge: charging and discharging output capacitance, overlapping voltage and current during the transition, and recovering the body diode of the synchronous switch. At 48 V input these losses scale with voltage and switching frequency. A designer is then forced to choose between a low switching frequency (large inductor, larger module) and a higher one (more loss, more heat). Removing the fan makes that trade-off harder.

Removing the fan moves the entire thermal budget onto conduction and natural convection — which only works if the converter dissipates very little and the heat path to ambient is short.

2. Why gallium nitride

2.1 Device-level advantages

GaN high-electron-mobility transistors (HEMTs) conduct through a two-dimensional electron gas instead of a silicon channel. For a power-conversion designer the relevant consequences are summarised in Table 1.

Table 1. GaN HEMT versus silicon MOSFET in a hard-switched half-bridge (qualitative, after [4]).

Parameter Silicon MOSFET Enhancement-mode GaN HEMT
Reverse-recovery charge (Qrr) Present (body diode) Zero: no minority-carrier body diode
Gate charge (Qg) Higher Much lower: lower drive loss, faster edges
Output charge (Qoss) Higher Lower: lower turn-on loss in hard switching
Reverse conduction in dead time Body-diode drop Channel conducts with VF ≈ Vth + |VGS(off)|; keep dead time short
Consequence in a buck converter Edge loss limits frequency and efficiency Lower loss per edge; efficiency and density can both rise

2.2 What this means in a synchronous buck

The absence of reverse-recovery charge removes the current spike and associated loss that occur when the high-side switch turns on against a conducting low-side device. Lower gate and output charge shorten the switching transition, which reduces overlap loss and allows a compact inductor without paying for it in efficiency. Because a GaN device in reverse conduction has a higher voltage drop than a silicon body diode [4], dead time must be kept as short as possible. The NP-0847 controller addresses this with smart near-zero dead-time control (section 3.2).

3. NP-0847 architecture

Figure 1. Functional block diagram of the NP-0847.
Figure 1. Functional block diagram of the NP-0847.

3.1 Power stage

The power stage is a synchronous buck converter. A ceramic (MLCC) input filter supplies the pulsed input current close to a half-bridge of two 100 V-class enhancement-mode GaN HEMTs. The switch node drives a low-loss power inductor, followed by a precision current-sense shunt and a ceramic output filter. All power components sit under a common aluminium heatsink (Figure 2).

3.2 Control and timing

A synchronous buck controller designed for GaN switches drives both HEMTs through integrated gate drivers. The design uses:

  • Fixed-frequency PWM at about 490 kHz with spread-spectrum modulation, which spreads conducted and radiated emission energy over a wider band.
  • Smart near-zero dead-time control, which minimises the time either GaN device spends in reverse conduction.
  • Pulse-skipping operation at light load, to keep light-load losses low.
  • Soft start of about 6.7 ms, to limit inrush current into the output capacitance.
  • Remote sense and resistor trim, so the regulation point can be placed at the load and the output set between 3.3 V and 15 V.

3.3 Sensing and protection

Inductor current is measured with a dedicated shunt rather than the inductor’s DC resistance. A shunt gives a sense signal that does not drift with inductor temperature, which makes short-circuit detection more consistent. The module provides current limiting for overload and short-circuit protection, input under-voltage lockout and an over-temperature shutdown driven by a temperature sensor mounted on the PCB (threshold above 100 °C) [1][2].

4. Thermal design

4.1 The natural-convection constraint

With no forced airflow, heat leaves the module through the pins into the host board and, mostly, from the heatsink to the surrounding air by natural convection and radiation. In natural convection the deciding factor is not fin area but whether cool air can reach the fin surface. A dense fin pattern that looks good on paper can trap air that is almost at metal temperature.

4.2 CFD-driven heatsink optimisation

Premium PSU ran a 3D conjugate CFD study (air and aluminium solved together, including convection and radiation) at the design dissipation of 5.19 W and 25 °C ambient [3]. Starting from a commercial straight-fin profile, 40 geometries were evaluated in five phases (starting profiles, interrupted fins, segmented fins, pins with gap equal to slot, and pin thickness), totalling 77 3D simulations. The workflow used open-source tools (OpenFOAM, gmsh, scikit-fem, ParaView and Python), with an AI agent automating geometry generation, simulation runs and result post-processing. The simulation model was validated against a measured prototype, with a deviation of +3.9 % [3].

Figure 3. CFD results: commercial straight-fin profile (a, b) versus optimised pin-fin array (c, d). Streamlines coloured by air temperature.
Figure 3. CFD results: commercial straight-fin profile (a, b) versus optimised pin-fin array (c, d). Streamlines coloured by air temperature.

The selected design (Q4) is an array of 48 pins of 1.38 × 1.32 mm with 3 mm gaps in both directions. The commercial profile had closed channels fed only from the ends, so air stagnated and heated almost to metal temperature. In the pin array, air enters from every side and crosses the pin matrix; with thinner pins, more air paths fit and the air between them runs 1.5 K to 2 K cooler [3].

Figure 4. Thermal resistance and mass: commercial profile versus CFD-optimised pin-fin heatsink [3].
Figure 4. Thermal resistance and mass: commercial profile versus CFD-optimised pin-fin heatsink [3].

Table 2. Heatsink comparison at 5.19 W, 25 °C ambient, natural convection [3].

Metric Commercial profile Optimised pin-fin (Q4) Change
Thermal resistance, heatsink to ambient 13.6 K/W 11.3 K/W −17 %
Heatsink temperature rise at 5.19 W Reference 12 K lower −12 K
Aluminium mass 24 g 15 g −40 %
Heat removed by convection / radiation 67 % / 33 % 71 % / 29 % —

Copper was evaluated and discarded. Conduction inside the heatsink is not the bottleneck: the temperature difference across the aluminium is only 2.5 K to 4 K. A copper base spreader gained 1.2 K; an all-copper heatsink gained 1.3 K but, unanodised, lost about 10 K through lower radiation and weighed 3.3 times more [3]. The production heatsink is anodised aluminium 6063-T5 [1].

5. Key specifications

Table 3. Main electrical, mechanical and environmental characteristics (preliminary, Gen1) [1].

Parameter Value Unit
Input voltage, nominal 24 / 48 V
Input voltage range 9 to 54 (VIN > VOUT) V
Turn-on input voltage 8 V
Output voltage (set with RTRIM) 3.3 / 5 / 12 / 15 V
Output current, continuous / peak (60 s) 20 / 27 A
Output power at 15 V, continuous / peak 300 / 405 W
Efficiency Up to 98 %
Line / load regulation, max. 0.5 / 1.3 %
Ripple and noise (20 MHz BW), max. 6 %pp
Dimensions (W × D × H) 33.0 × 22.9 × 30 mm
Footprint 1/16th brick, through-hole pins —
Operating / storage temperature −40 to 50 / −55 to 85 °C
Cooling Natural convection —
Relative humidity 5 to 95 %
MTBF > 10 Mh

Power density, counting the heatsink, is about 13 W/cm³ (300 W in 22.7 cm³), derived from the figures above.

6. Designing in the NP-0847

6.1 Pinout and footprint

Table 4. Pin functions [1].

Pin Function Notes
1 VIN (+) Input positive
2 ON/OFF Remote enable
3 VIN (−) Input return
4 VOUT (−) Output return, power pin
5 PWR GOOD Open-drain status; pull up externally (10 kΩ to 3.3 V)
6 TRIM Output voltage adjustment
7 SENSE (+) Remote sense at the load
8 VOUT (+) Output positive, power pin

6.2 Output voltage trim

The output is set by a single resistor RTRIM between TRIM and VOUT (−). Standard values are given in Table 5.

Table 5. Trim resistor for standard output voltages [1].

VOUT (V) RTRIM (kΩ)
3.3 Open
5 11.3
12 2.15
15 1.58

6.3 Typical application circuit

  • Place a 100 µF input capacitor between VIN (+) and VIN (−), close to the module.
  • Place 0.1 µF ceramic and 22 µF capacitors at the output. Connect SENSE (+) at the load for best regulation.
  • Pull PWR GOOD up to the logic rail (10 kΩ to 3.3 V in the reference circuit).
  • The module has no reverse-polarity protection: add it externally if the input can be reversed in the application.
  • Keep VIN above VOUT; minimum operating input is 9 V and the module turns on at 8 V.
  • Allow free vertical airflow around the heatsink: the thermal design relies on air entering the pin array from all sides.

7. Safety, environment and reliability

  • Safety: designed according to IEC 62368-1, pollution degree PD2, overvoltage category OV2 [1].
  • Environmental compliance: RoHS according to Directive (EU) 2015/863 and REACH [1].
  • Reliability: predicted MTBF above 10 million hours [1].
  • Protection: current limiting for overload and short circuit, input under-voltage lockout, over-temperature shutdown.

Conclusion

The NP-0847 shows that GaN switching and simulation-driven thermal design together let a 1/16th-brick converter deliver 300 W without a fan. GaN removes reverse-recovery loss and shortens every switching edge; near-zero dead-time control keeps reverse-conduction loss low; and a CFD-optimised pin-fin heatsink takes the remaining heat to ambient with 17 % lower thermal resistance and 40 % less aluminium than a catalogue profile. For the system designer, the result is a standard-footprint module with the control and protection functions expected of a brick, and one less moving part in the system.

To evaluate the NP-0847 in your application, contact the Premium PSU engineering team through www.premiumpsu.com.

Download the full white paper (PDF)

Includes the complete specification tables, pinout, hole pattern, trim table and the recommended application circuit for the NP-0847.

Download PDF

References

  • [1] Premium PSU, CA-762-C Datasheet NP-0847 (Gen1), ed. 3, 2026-08-05.
  • [2] Premium PSU, Schematic SCH-NP0847 – Buck Converter BRICK, rev. B, 2026-10-14 (internal).
  • [3] Premium PSU, GaN heatsink: from commercial profile to CFD-optimised design, internal study (OpenFOAM), 2026 (available on request).
  • [4] GaN Systems, GN001 Application Guide: Design with GaN Enhancement Mode HEMT, 2018-02-28. https://gansystems.com
  • [5] IEC 62368-1, Audio/video, information and communication technology equipment – Part 1: Safety requirements.
  • [6] Commission Delegated Directive (EU) 2015/863 amending Annex II to Directive 2011/65/EU (RoHS).
About Premium PSU — Premium PSU is one of the largest power supply companies in Europe, offering solutions to the industrial market, some of them in high-tech machinery, transportation, energy or extreme-environment applications. Founded in 1991, Premium designs and manufactures power conversion systems for customers all around the world. Premium PSU’s power range includes DC/DC converters, uninterruptible power supplies, DC/AC inverters, AC/DC power supplies and any solution that requires high reliability from 50 W to 72 kW. Custom is Premium PSU’s standard, so any current product variation or new development can be done by our R&D department, a team of over 50 engineers with a wide know-how. All products comply with the specifications and regulations that each application requires, and all projects, from concept and design until the homologation of the product, are carried out in Barcelona under strict quality controls.
simulating
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Simulation and Test Tools That Ensure Success from the First Delivery

Engineering Insight · Technical Article

Simulation and Test Tools That Ensure Success from the First Delivery

How Premium SA builds custom power supplies and conversion systems that work at the first prototype

Premium SA
Born in Barcelona, Powering the World
4
Simulation layers
≥6 dB
EMC design margin
3 units
DVT, zero rework
RPN > 100
FMEA verification trigger

Executive summary

The custom power electronics project for critical sectors — railway, defence, energy, infrastructure — does not allow the iterative cycle of the catalogue product. Production runs are short, deadlines are contractually binding, and the first prototype delivered to the customer must operate within specification. Massive hardware iteration is not an economically or temporally viable option.

Premium SA has developed an integrated simulation and test chain that systematically reduces the risk of the first prototype. The philosophy is direct: each hour of well-formulated simulation saves between five and ten hours of physical bring-up, and every fault detected in the modelling phase prevents costs that multiply exponentially when they appear in production or in the field.

The D2x methodology: five phases, one chain. The chain is built upon Premium SA’s proprietary D2x methodology — D2W (Design to Win), D2F (Design to Fabrication), D2C (Design to Cost), D4R (Design for Reliability) and D4Co (Design for Compliance / Component) — with quantitative stage-gates between phases and a V-Model that links each requirement with its verification evidence.

1. The custom project challenge: no second chance

Custom equipment is born from a tender specification: 15 kV DC in a railway substation, passive cooling in a deployable defence converter at −40 °C, a form factor for a traction cabin that does not allow a single additional millimetre. Each of these requirements eliminates entire families of catalogue solutions and forces design from the topology level upwards.

The operational consequence is severe: the first prototype delivered to the customer — typically between week four and week six of the project — is validated against the entire contract, not against a simplified version. Any deviation appearing in that validation has three possible outcomes, all costly: partial redesign with timeline replanning, acceptance of contractual penalties, or batch rejection with replacement.

Production runs are short — 50 to 500 units is a typical range in railway and defence — and the product learning curve runs out before it covers the cost of iteration. Success at the first prototype is not a desirable goal; it is the minimum threshold of economic viability.

The key metric: first-pass DVT approval rate. In projects where stages are shortened due to schedule pressure, this indicator drops rapidly and drags timelines and margins with it. Applying the simulation chain in full is what protects it.

2. The pre-prototype simulation chain

Pre-hardware verification is structured in four layers covering the four dominant fault vectors in power electronics: electrical behaviour in transients, thermal dissipation, electromagnetic compatibility and digital control. The four layers run in parallel and intersect at quantitative validation points.

2.1 Electrical modelling: SPICE / PLECS / Simulink

The first layer is the power circuit model. Standard tools — SPICE for detailed switching analysis, PLECS or Simulink for averaged models and full-system simulation — allow verification, before manufacturing the first PCB, that the closed control loop is stable across the full operating range, that waveforms at critical nodes do not exceed semiconductor voltage margins, and that calculated losses are consistent with the available thermal dissipation.

For topologies using wide-bandgap semiconductors (SiC, GaN), accurate modelling of packaging parasitic effects is decisive. A use case of the European ALL2GaN research project has documented how the parasitic inductance of the power loop conditions snubber sizing in 3 kW/48 V totem-pole rectifiers achieving 97.5% efficiency and 40 W/in³ density: without an electrical model that captures the inductance of the TOLL package versus PG-DSO-20, the sizing falls outside the optimum.

2.2 Thermal CFD simulation: from chip to system

The second layer covers the thermal domain. CFD simulation enables characterisation at three levels of detail: chip-level dissipation and junction-to-case of the semiconductor; air or liquid circulation in the complete product; and heat transfer with the environment — cabin, cabinet, outdoor. We cover this domain in more detail in our article on thermal design in power electronics.

For demanding power densities — current OCP servers for AI workloads must dissipate hundreds of kilowatts per rack, with the most demanding variants approaching local heat fluxes above 700 W/cm² in active areas — integrated liquid microchannel solutions with dielectric coolant, in fraction-of-a-millimetre channel geometries, are already production-ready technology.

Cross-validation between the electrical model (which delivers the loss map per component) and the thermal model (which delivers the temperature map) closes the first cycle: an operating point with plausible losses but unacceptable temperature forces a topology revision, not an oversizing of the dissipation.

2.3 EMC pre-compliance simulation

The third layer is electromagnetic compatibility. A pre-compliance session in a semi-anechoic chamber typically costs several thousand euros and consumes calendar days; discovering a radiated-emissions failure at that stage, with the product already wired, is one of the most damaging scenarios for a custom project.

Modern EMC simulation tools — Method of Moments (MoM) solvers for radiated emissions, cable-bundle models for conducted emissions, PCB-specific simulators for ground-plane resonances — allow prediction of product behaviour against the applicable standards (CISPR 32, EN 50121-3-2 for railway, MIL-STD-461 for defence) before manufacturing. The Premium SA criterion sets a minimum design margin of 6 dB with respect to the applicable limits; any spectrum point that falls inside that margin in simulation triggers a design iteration before manufacturing.

2.4 MATLAB / Simulink: digital control validation

The fourth simulated layer covers the digital control loop. MATLAB and Simulink allow verification of the stability of voltage, current and temperature loops across the full load range, identification of operating points with insufficient phase margin, and sizing of compensators before implementing them in firmware. Automatic C code generation from the Simulink model reduces the risk of discrepancy between what is simulated and what is deployed.

This layer becomes particularly relevant when control must be certified at functional safety level — SIL2 or SIL3 according to EN 50128 for railway, ASIL-B or ASIL-C according to ISO 26262 for automotive. Traceability between the safety requirement, the Simulink model, the generated code and the associated test is both a normative requirement and a quality practice.

3. Quantitative reliability analysis: D4R

Reliability is not only verified on the bench; it is designed. Quantitative reliability analysis — embodied at Premium SA in the D4R methodological block — makes it possible to commit to MTBF figures backed by model and evidence. Our white paper on reliability in critical power electronics develops this approach further.

3.1 MTBF calculation

MTBF calculation at Premium SA follows the standards accepted by each sector: Telcordia SR-332 (formerly Bellcore) and MIL-HDBK-217F for the Anglo-Saxon and defence markets; Siemens SN29500 for European industrial customers; IEC 61709 when required by the customer; FIDES for sectors with particular environmental severity requirements.

For topologies using wide-bandgap semiconductors, derating factors are particularly relevant. SiC allows junction operation at 200 °C, and GaN between 175 °C and 200 °C; however, standard practice in custom projects is to work with a derating of 30 to 50% on datasheet limits. The difference between operating a SiC MOSFET at Tj = 150 °C versus Tj = 175 °C, all else being equal, roughly doubles the failure rate.

3.2 FMEA: systematic risk ranking

FMEA is applied to both product design (Design FMEA) and the manufacturing process (Process FMEA). For each identified failure mode, three dimensions are assessed — severity, probable occurrence and detectability — giving a Risk Priority Number (RPN) as the product of the three. Premium SA practice sets two thresholds: no failure mode with severity 9 or 10 (out of 10) can leave the FMEA without documented corrective action, and any mode with an RPN above 100 enters the verification plan with a specific test.

3.3 FTA: top-down tree from the effect

Fault Tree Analysis works in the opposite direction to FMEA: it starts from a feared event — loss of power output, dangerous voltage emission to the load — and descends to identify the combinations of elementary failures that can produce it. The quantitative analysis, fed with component failure rates, allows calculation of the probability of the feared event and verification that it meets contractual or normative objectives — a PFH below 10−7 for SIL3, for example. FMEA and FTA are complementary: FMEA is exhaustive bottom-up; FTA is analytical top-down.

4. Physical testing: DVT, HALT and HASS

Simulation reduces uncertainty but does not eliminate it. The physical test plan closes the flow by verifying model predictions against reality and characterising the product against failure modes the model does not capture.

4.1 DVT: Design Verification Testing

DVT is the complete verification battery for the contractual product requirements: nominal and transient electrical behaviour, output regulation across the full load range, thermal behaviour under nominal and derating conditions, EMC margins with respect to the applicable standard, mechanical tests — vibration, shock, thermal cycling — and behaviour under simulated environmental faults. Standard practice runs DVT on three units; all three must pass all tests without rework.

4.2 HALT and HASS: accelerated filters

HALT (Highly Accelerated Life Testing) takes the product beyond operational conditions — temperature ramps between −80 °C and +120 °C with simultaneous six-axis vibration — to identify operational and destructive margins. The purpose is to dramatically accelerate the appearance of latent failures so they can be corrected before series production.

HASS (Highly Accelerated Stress Screening) applies the knowledge gained in HALT as a production filter: each manufactured unit is subjected to an accelerated profile (typically 50 to 80% of the operational margin identified in HALT) to discard units with latent defects before shipping. The HALT+HASS combination does not replace DVT; it complements it.

5. The D2x methodology as structural framework

The previous layers only add value if applied at the right time and with the right criterion. The D2x methodology structures this flow: each of the five phases has an assigned set of simulation and test activities, with quantitative stage-gates between phases that are crossed only when the criteria are met.

“The stage-gate turns the methodology into discipline, not intention. A phase does not close because the calendar has passed; it closes because the metric has been met.”

The V-Model that structures the methodology links each requirement in the descending branch with its corresponding verification phase in the ascending branch. For safety-critical software, the V-Model is a normative requirement: EN 50128 prescribes it for railway software classified SIL1 to SIL4; ISO 26262 for automotive ASIL-A to ASIL-D; and IEC 61508 is the umbrella standard for industrial functional safety.

6. Conclusion

“In custom projects, success at the first prototype is not a goal; it is the minimum threshold of viability. Premium SA has built the simulation and test chain that turns that threshold into reproducible practice.”

The chain described — four layers of simulation, three quantitative reliability tools, two levels of accelerated testing, all structured by the D2x methodology — is Premium SA’s operational answer to a structural constraint: the first prototype must work.

For the customer engineer evaluating providers of custom power electronics, the relevant question is not whether the supplier knows how to design; it is whether the supplier knows how to verify.

References

Standard / document Scope
Telcordia SR-332 (Issue 4) Reliability prediction — electronic equipment
MIL-HDBK-217F Notice 2 Reliability prediction — defence
Siemens SN29500 Failure rates — European industrial
FIDES Guide 2022 Reliability methodology — complex environments
IEC 61508 Functional safety — industrial
EN 50128:2011 Railway software — SIL1 to SIL4
ISO 26262 Automotive functional safety — ASIL-A to ASIL-D
CISPR 32 EMC — multimedia equipment
EN 50121-3-2 EMC — railway rolling stock
MIL-STD-461 EMC — defence equipment

Talk to our engineering team

Facing a demanding custom specification? Our engineering team can show you how the simulation, reliability and test chain is applied to your converter from the first design gate.

Contact Premium SA

About Premium SA

Premium SA (Premium PSU) is a Barcelona-based designer and manufacturer of custom power supplies and power converters for railway, energy, industrial, data centre and defence applications, with over 40 years of experience since its foundation in 1981. Born in Barcelona, Powering the World.

© 2026 Premium SA · Barcelona, Spain · Born in Barcelona, Powering the World
fuse

Real 5-year TCO: conventional fuse vs. eFuse in a 50-circuit 24 V DC industrial cabinet

White Paper · TCO Analysis

Real 5-year TCO: conventional fuse vs. eFuse in a 50-circuit 24 V DC industrial cabinet

Total cost of ownership of two 24 V DC circuit protection schemes in a representative industrial scenario

€7,994.50
Net saving over 5 years
14 months
eFuse payback
321%
5-year ROI
−82%
Cost reduction per event

Executive summary

This analysis compares the 5-year total cost of ownership (TCO) of two 24 V DC circuit protection schemes in a representative 50-channel industrial cabinet: conventional gG fuses vs. electronic fuses (eFuses) with LED signalling. The scenario assumes 6 fault events per year, a line downtime cost of €500/hour and technician labour at €65/hour. Result: the eFuse pays back its additional cost in 14 months and delivers a net saving of €7,994.50 over the 5-year horizon compared with the conventional fuse.

If you are new to this technology, we recommend starting with our introduction: what an electronic fuse (eFuse) is and why it is replacing conventional fuses in industrial control panels.

1. Definition of the analysis scenario

The analysis is based on an industrial installation representative of typical projects in the Spanish market: a production line with a control cabinet feeding 50 independent 24 V DC circuits (sensors, actuators, valves, small motors and drives). The scenario parameters are detailed below:

Scenario parameter Value used Source / rationale
Number of 24 V DC circuits 50 channels Typical industrial automation cabinet
Current per channel Mixed: 25× at 2 A, 15× at 4 A, 10× at 6 A Typical loads: sensors, valves, small motors
Circuit fault events / year 6 events Conservative estimate for an industrial environment with moderate EMC
Line downtime cost (€/hour) €500/hour Discrete manufacturing: typical range €200–2,000/hour
Technician labour cost (€/hour) €65/hour Qualified industrial electrician, Spain 2025
Analysis horizon 5 years (60 months) Typical life cycle of cabinet equipment
Discount rate 0% (nominal analysis) Conservative simplification; the eFuse advantage is greater with discounting

2. TCO of the conventional fuse

2.1 Initial investment costs

The material cost of protecting 50 channels with conventional fuses includes fuse holders, fuses of different ratings and the initial spare-parts stock:

Item Quantity Unit price (ref.) Subtotal
DIN rail fuse holders (per channel) 50 pcs €4.50 €225
gG 2 A fuses (25 channels) 25 pcs + 10 spare €0.80 €28
gG 4 A fuses (15 channels) 15 pcs + 6 spare €0.90 €19
gG 6 A fuses (10 channels) 10 pcs + 4 spare €1.10 €15
Installation labour (5 h × €65) 5 hours €65/h €325
Total initial investment €612

2.2 Annual operating costs

Each conventional fuse fault event in this scenario involves three types of cost: diagnosis (locating the blown fuse), line downtime and fuse replacement. The average diagnosis time in a 50-circuit cabinet without fault signalling is 45 minutes.

Cost component per event Time / qty Unit cost Cost / event Annual cost (6 ev.)
Diagnosis and location (technician) 45 min €65/h €48.75 €292.50
Line downtime (production stopped) 45 min €500/h €375.00 €2,250.00
Fuse replacement + stock 1 pc €1.00 €1.00 €6.00
Total cost per event → annual €424.75 €2,548.50
Conventional fuse TCO summary Amount 5-year cumulative
Initial investment (material + installation) €612 €612
Year 1 — fault events €2,548.50 €3,160.50
Year 2 €2,548.50 €5,709.00
Year 3 €2,548.50 €8,257.50
Year 4 €2,548.50 €10,806.00
Year 5 €2,548.50 €13,354.50
Total 5-year TCO — conventional fuse €13,354.50

3. TCO of the electronic fuse (eFuse)

3.1 Initial investment costs

Protecting 50 channels with eFuses requires 13 four-channel modules (12 full modules + 1 for the remaining 2 channels). A competitive module from the European market is used as the price reference (mid-to-high range, with per-channel LED signalling and adjustable current from 1 to 10 A):

Item Quantity Unit price (ref.) Subtotal
4-channel 24 V eFuse modules (mid-to-high range) 13 modules €200.00 €2,600
24 V/20 A DIN rail power supply (common supply) 2 pcs €120.00 €240
Installation labour (4 h × €65) 4 hours €65/h €260
Total initial investment €3,100
Note: eFuse installation labour is slightly lower than for conventional fuses because there is no need to install 50 individual fuse holders; the 4-channel modules connect more quickly to the DIN rail with push-in or standard screw terminals.

3.2 Annual operating costs

With the eFuse installed, the diagnosis process changes radically. The red LED of the faulty channel is visible on the front of the module without opening the cabinet. In installations with SCADA, the digital alarm signal indicates the exact channel in the supervision system. The average diagnosis time drops to 8 minutes. Reset is manual (push-button) or automatic depending on configuration; this scenario assumes manual mode for greater operator control.

Cost component per event Time / qty Unit cost Cost / event Annual cost (6 ev.)
Diagnosis and location (technician) 8 min €65/h €8.67 €52.00
Line downtime (production stopped) 8 min €500/h €66.67 €400.00
Component replacement 0 (none) €0 €0 €0
Total cost per event → annual €75.34 €452.00
Electronic fuse (eFuse) TCO summary Amount 5-year cumulative
Initial investment (modules + power supply + installation) €3,100 €3,100
Year 1 — fault events €452.00 €3,552
Year 2 €452.00 €4,004
Year 3 €452.00 €4,456
Year 4 €452.00 €4,908
Year 5 €452.00 €5,360
Total 5-year TCO — eFuse €5,360

4. Comparison and return analysis

Metric Conventional fuse Electronic fuse (eFuse)
Initial investment €612 €3,100
Annual operating cost (6 ev./year) €2,548.50 €452.00
3-year TCO €8,257.50 €4,456
5-year TCO €13,354.50 €5,360
Net saving over 5 years — €7,994.50
Break-even point (payback) — 14 months
Diagnosis time reduction Baseline (45 min) −82% (8 min)
Cost reduction per event Baseline (€424.75) −82% (€75.34)
Component replacement / year 6 fuses 0 (no consumables)

The eFuse pays back its additional investment of €2,488 (€3,100 − €612) in 14 months thanks to annual savings of €2,096.50 in diagnosis and downtime costs. Over the 5-year horizon, every additional euro invested in the eFuse returns €3.21 in net savings. The 5-year ROI on the additional investment is 321%.

5. Sensitivity of the result: when does the eFuse NOT pay off?

The analysis above assumes 6 fault events per year and a downtime cost of €500/hour. It is important to understand how the conclusion changes with different parameters:

Scenario Events/year Downtime cost (€/h) eFuse payback Conclusion
Continuous production (baseline) 6 €500 14 months eFuse clearly cost-effective
High fault frequency 12 €500 7 months eFuse highly cost-effective
Very costly downtime (data centre) 4 €2,000 6 months eFuse highly cost-effective
Low-demand installation 2 €200 91 months (about 7.5 years) Does not pay back within 5 years
Simple installation, few stoppages 1 €100 >10 years Conventional fuse more economical

The rule of thumb is as follows: if an installation with 50 circuits at 24 V DC suffers 2 or fewer fault events per year and the downtime cost is €200/hour or less, the conventional fuse may be economically preferable over a 5-year horizon. In all other typical industrial scenarios, the eFuse is the more cost-effective option.

The eFuse break-even threshold falls significantly in installations where remote monitoring of circuit status has independent added value (SCADA integration, predictive maintenance, compliance with functional safety requirements). In those cases, the eFuse with IO-Link is compared against the cost of installing a separate monitoring system — and generally comes out ahead.

6. Methodology and limitations of the analysis

This analysis is based on a representative industrial scenario, not on a specific real installation. The unit prices of the eFuse modules are indicative and vary by manufacturer, purchase volume and channel agreement. The operating cost parameters (downtime, labour) are estimates based on Spanish industrial sector references for 2025–2026.

  • Diagnosis costs assume a single technician working without additional remote diagnostic tools. Installing SCADA or an additional telemetry system would reduce diagnosis time with conventional fuses, changing the differential.
  • The analysis does not include the benefits of selective protection (preventing a fault in one channel from affecting adjacent channels), which in high-criticality installations can represent significant additional value.
  • Line downtime costs have the greatest influence on the final result. Each company should apply its own downtime cost to obtain an accurate estimate of its specific payback.

Want to calculate the TCO of your installation?

Share the real parameters of your cabinet and our engineering team will help you evaluate the protection of your 24 V DC circuits.

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About Premium SA — Founded in Barcelona in 1981, Premium SA designs and manufactures high-reliability custom power supplies and protection systems for industrial automation, energy and critical applications, with over 40 years of experience in custom power electronics.
white paper

White paper – 40+ Year Reliability in Critical Power Electronics

White Paper · Reliability & RAMS

40+ Year Reliability in Critical Power Electronics: The Premium SA Approach

Physics-of-Failure, DFR methodology, RAMS metrics and PHM — for directors of engineering, procurement and operations

Premium SA
Born in Barcelona, Powering the World
<30%
Acquisition Cost Share of TCO
>10⁶ h
MTBF on Standard Platforms
4 gates
DFR Sequential Quality Gates
+40 yr
Spares Support Commitment

Introduction: From Unit Price to Total Cost of Ownership

White paper – 40+ Year Reliability in Critical Power Electronics

In critical infrastructure — rolling stock, electrical substations, signalling systems, continuous-process plants — the cost of one hour of unavailability far exceeds the price of any electronic converter. Over the last decade, the fraction of total cost of ownership attributable to the acquisition price has fallen below 30% in railway and substation grid applications; the remaining 70% is split between energy consumed, scheduled maintenance, spare parts and, above all, unavailability.

The result is that the purchase decision has migrated from unit price to total cost of ownership. The real question is no

longer “how much does it cost?” but “how long will it last and how will you prove it?”

1. Why Power Electronics Fails — The Physical Mechanisms

Electronic components do not fail randomly: they fail through identifiable, modellable and predictable physical mechanisms. The Physics-of-Failure (PoF) methodology — which Premium SA adopts as primary reference, as opposed to the outdated MIL-HDBK-217F — classifies these mechanisms into four families:

1. Thermo-Mechanical Mechanisms

Dominant in power modules (IGBT, MOSFET, SiC). Every thermal cycle causes materials with different coefficients of thermal expansion (CTE) to expand and contract at different rates, accumulating plastic deformation in solder joints and bond wires.

  • Solder fatigue: Coffin-Manson model: Nf ∝ ΔTj−n with n ≈ 5–7. Increasing Rth(j-c) → vicious circle of rising Tj and accelerating degradation
  • Wire-bond lift-off: Main cause of wear-out failure in traction IGBT modules. Each lost wire increases current in remaining ones, accelerating the next failure

2. Electrical & Dielectric Mechanisms

Active semiconductors age through electrical causes, with no need for thermal cycles. Degradation accumulates during normal operation.

  • TDDB: Gate oxide traps accumulate until resistive conduction path forms. Arrhenius model with electric field accelerator
  • Electromigration: Black model with J² as main variable. Opens voids or creates shorts in metallisation traces
  • Hot Carrier Injection (HCI): Particularly relevant in fast-switching SiC and GaN transistors
  • NBTI/PBTI: Gradual transconductance gm reduction under bias at high temperature

3. Chemical & Environmental Mechanisms

Humidity, contaminants, salts and radiation present in any real installation.

  • Corrosion and electrochemical migration: Dendrite formation (whisker effect) causing intermittent shorts. Peck model (humidity × temperature)
  • Radiation-induced errors (SEU): Cosmic ray neutrons and alpha particles causing Single Event Upsets in memory cells. Mitigated by design: ECC, watchdogs, logical redundancy

4. Mechanical Mechanisms

In railway applications under EN 61373 (category 1B body-mounted), equipment absorbs 5–50 m/s² of random vibration over full life. Critical points: solder joints of heavy components (electrolytics, ferrites, transformers) and connectors. Design control: first mechanical PCB frequency clearly above dominant excitation range (>75 Hz).

2. The Bathtub Curve — Each Phase Calls for a Different Technique

Electronic components exhibit three recognised phases: infant mortality (high initial failure rate from latent manufacturing defects), useful life (low and approximately constant rate), and wear-out (rising rate from accumulation of physical mechanisms). A mature DFR process attacks all three simultaneously.

Technique Phase Addressed When Applied Premium SA Standard
HALT (Highly Accelerated Life Testing) Design margin discovery Design phase on prototypes Combined temperature + vibration stresses beyond specification limits
HASS (Highly Accelerated Stress Screening) Latent manufacturing defects Production screening Stress levels just below operating limit; 100% of production units
Burn-in Infant mortality (left tail) Post-production, pre-delivery 4 h per unit at +60 to +80 °C; extendable to 8 h for long-interval programmes

3. RAMS — The Contractual Language of Reliability

RAMS stands for Reliability, Availability, Maintainability, Safety — the four metrics with which a railway operator or grid DSO measure equipment suitability over its useful life. EN 50126 is the framework standard; EN 50128 and EN 50129 cover software and functional safety respectively.

Reliability

R(t) — probability of surviving to time t. Expressed as MTBF = 1/λ for exponential distribution, or by Weibull parameters (β, η) for wear-out phases. Premium SA calculates MTBF by PoF, not by parts-count (MIL-HDBK-217F).

Availability

A = MTBF / (MTBF + MTTR). For a substation converter with MTBF = 500,000 h and MTTR = 4 h: A ≈ 99.9992%. The key lever is not only increasing MTBF but also reducing MTTR.

Maintainability

Design levers: LRU architecture (front access, two captive screws, keyed connectors), built-in telemetry and self-test, RUL (Remaining Useful Life) estimation via PHM, and 40+ year spares continuity with quarterly obsolescence review.

Safety — EN 50128 / 50129

SIL (Safety Integrity Level) per IEC 61508. PFD (Probability of Failure on Demand) for standby safety functions. SIL 3–4 requires: redundancy, periodic self-test, MC/DC software coverage metrics, formal methods. Premium SA D4Co-SW methodology aligned with EN 50128.

4. The Premium SA DFR Process — Four Sequential Gates

The Design for Reliability (DFR) methodology — originated at the Center of Reliable Power Electronics (CORPE, Aalborg University) and adopted as an internal standard at Premium SA — structures development in four sequential gates with quantitative exit criteria:

Gate Objective Key Activities Exit Criterion
D2W (Design to Work) Functional specification Mission profile definition, requirements capture, architecture selection Signed mission profile + functional test pass
D2F (Design to Function) Derating and PoF analysis Tj_max ≤ 80%, Vop ≤ 80%, thermal simulation, stress analysis All derating targets met; no RPN > 80 open
D4R (Design for Reliability) FMEA, FTA, HALT FMEA bottom-up + FTA top-down; HALT protocol; Coffin-Manson solder analysis RPN > 100 blocked; HALT limits documented; MTBF target verified
D4Co (Design for Compliance) Qualification and FRACAS HASS production screening; burn-in; EMC pre-compliance; EN 50155/EN 61373 qualification All certifications obtained; FRACAS activated; customer RAMS deliverables signed

5. FMEA, FTA and the Analytical Hierarchy

Once derating is established, reliability engineering identifies and mitigates dominant failure modes through three complementary analyses:

  • FMEA/FMECA (Failure Mode and Effects Analysis): Bottom-up. RPN = Severity × Occurrence × Detection (1–10 scale). At Premium SA, any RPN >80 triggers a documented action plan; RPN >100 blocks the D4Co gate.
  • FTA (Fault Tree Analysis): Top-down. Decomposes boolean combinations (AND/OR gates) that may cause system fault. Quantifies impact of redundancies; allows calculation of system-level MTBF.
  • ETA (Event Tree Analysis): Inductive. Models scenarios and responses derived from a single initiating event. Useful for evaluating fault propagation in multi-state systems.

6. Keeping Reliability in Service — PHM, FRACAS and Lean Reliability

PHM — Prognostics and Health Management

The active technical frontier today is the transition from fixed-schedule preventive maintenance towards maintenance based on actual condition. In Premium SA converters:

  • Real-time Tj estimation of semiconductors from Vce_sat and current, with case-temperature compensation
  • Cumulative power-cycle counting with associated ΔTj, to predict RUL (Remaining Useful Life) by PoF models
  • ESR monitoring of capacitors by ripple analysis
  • Periodic export of operating data over communication bus to the operator’s supervisor, with P-F (potential-functional) profile

FRACAS — The Continuous-Learning Loop

Failure Reporting, Analysis and Corrective Action System: every field return is analysed at the appropriate level — LRU, board, component — root cause is identified, and the corrective action is propagated to design and production. The consequence is that the population of installed equipment improves over time rather than degrading. The problem detected in unit #150 is prevented in unit #151.

About Premium SA — Premium SA is a Barcelona-based manufacturer of power electronics converters for railway, industrial and energy applications. Founded in 1981, with more than 900 standard product designs and over 40 years of operational experience, Premium SA supplies DC/DC converters, DC/AC inverters, AC/AC frequency converters, battery chargers, rectifiers and UPS systems from 50 W to 72 kW. All products are designed and manufactured at the Premium SA plant in Barcelona, with capability for EN 50155, EN 50121-3-2, EN 45545-2 and EN 61373 certification. Premium SA serves OEMs and system integrators across Europe through direct sales and a network of specialist distributors — ELIPSE (Benelux), Elma Electronic (Switzerland), RELEC Electronics (United Kingdom), DACPOL (Poland and Central Europe) and ANDA-OLSEN (Scandinavia).

Premium SA  ·  Barcelona, Spain  ·  info@premiumpsu.com  ·  +34 932 232 685  ·  www.premiumpsu.com

© 2026 Premium SA · All rights reserved · Barcelona, Spain
Born in Barcelona, Powering the World
white paper

White paper – From geometry to the watt

Technical White Paper — Power Conversion Strategy

From geometry to the watt

Huawei’s temporal scaling (Tau Law and LogicFolding) and why high-voltage power delivery, close to the chip, becomes the new frontier of performance, efficiency and infrastructure cost.
Premium PSU
|
PRM-WP-2026-014
|
v1.0 · Technical draft
|
R&D · Energy · Data Center · e-Mobility
|
Internal / Partners under NDA

+53.5%
transistor density (up to 238 M/mm²)
+40%
energy efficiency in main cores
+12.7%
maximum clock frequency (up to 3.1 GHz)
1.4nm
equivalent density it aims to reach by 2031

 

0 — Executive summary
The constraint that shifts the frontier toward power

At ISCAS 2026 in Shanghai, Huawei proposed replacing the geometric scaling of Moore’s Law with temporal scaling: optimizing the time a signal takes to propagate through the chip (the τ constant) instead of transistor size. Its LogicFolding architecture aims to gain density and performance through 3D integration and shorter critical paths, on mature nodes that China can actually manufacture.

For Premium, what matters is not the dispute over whether τ deserves to be called a “law”. It is the inevitable physical consequence of any path that stacks more logic into less volume — whether from Huawei, TSMC, Apple or NVIDIA: power density rises, heat concentrates, and the performance ceiling is no longer set by the transistor but by the ability to deliver clean energy to the die and extract the resulting heat.

When scaling is measured in time rather than size, the bottleneck moves from the lithographer to the power engineer. High-voltage energy delivery, with conversion as close to the load as possible, goes from being infrastructure to being a lever for performance and cost.

This document traces that causal chain across four derivatives — energy consumption, performance, heat extraction and voltage architecture — and places Premium’s opportunity at the center of the last three.

1 — The paradigm shift
What Huawei proposed, and what is real about it

On May 25, 2026, He Tingbo — president of Huawei’s semiconductor business — presented the Tau (τ) Scaling Law and two supporting technologies: LogicFolding, which folds 2D circuits into vertical 3D stacks to shorten critical-path wiring, and UnifiedBus, a protocol to reduce communication latency at system level.

The core idea is sound and not new in itself: below ~10 nm, interconnect delay (the RC constant of the wiring) dominates over gate delay. The entire industry is already moving toward system scaling — backside power delivery, 3D stacking, hybrid bonding, the CFET roadmap. What Huawei does is turn that axis into corporate doctrine, because sanctions (no EUV lithography from ASML since 2023) close off the geometric axis.

Critical reading: “1.4 nm-equivalent density” is not being at 1.4 nm. It is functional density through stacking, and stacking shifts the problem — it does not eliminate it — toward three fronts that are precisely the domain of power electronics and thermal engineering:

  • Volumetric power density: more active logic in fewer mm³.
  • Current delivery: feeding the inner layers of a 3D stack without the power distribution network (PDN) “choking” them.
  • Heat dissipation: extracting heat from the interior of a solid, not just from a surface.

In other words: Huawei’s path, just like its rivals’, increases the strategic value of advanced power conversion and cooling. The rest of this document explains why.

2 — Derivative I · Energy consumption
Two layers of energy: the one that computes and the one lost along the way

The energy consumption of a computing system splits into two layers with very different dynamics:

Compute layer (on the die)

Dynamic energy follows approximately P ≈ α·C·V²·f. Reducing τ and wiring length lowers the effective capacitance C and allows, for the same frequency, operation at a lower voltage V — and the dependence on V is quadratic. This is where LogicFolding’s claimed +40% efficiency lives. It is a real gain, but confined to the chip.

Distribution and cooling layer (off the die)

At rack and data-center scale, a growing fraction of the energy never gets to compute: it is lost in voltage conversions, in distribution (I²R losses) and in moving heat (cooling overhead, reflected in PUE). As AI accelerators scale from hundreds of watts to several kilowatts per package, this second layer dominates total cost of ownership.

The efficiency the circuit designer gains inside the die can be lost — multiplied — in the power and cooling chain if the voltage architecture does not evolve at the same pace. That is Premium’s space.

3 — Derivative II · Performance
The performance ceiling is, increasingly, a power ceiling

Temporal scaling explicitly acknowledges that modern performance — and AI performance in particular — is limited by data movement, not transistor count. UnifiedBus and LogicFolding attack that “memory wall”. But there is a second wall, physical and less discussed:

  • A chip can only switch as fast as it can be fed. Increasingly aggressive current transients (di/dt) demand a very-low-impedance PDN and point-of-load (PoL) regulators millimeters from the silicon.
  • A chip can only sustain its frequency as long as it can be cooled. Thermal throttling is the most direct way a cooling shortfall turns into lost performance.

Thus, the +12.7% frequency that LogicFolding promises only materializes in the field if power delivery and thermals keep up. Delivered performance is the minimum between what the silicon can do and what the power infrastructure allows it to do.

4 — Derivative III · Heat extraction
From a surface problem to a volume problem

3D stacking changes the nature of the thermal problem. A planar chip dissipates power per unit of surface (W/cm²); a 3D stack concentrates it per unit of volume (W/cm³), and the inner layers sit far from any heat-exchange surface. The progression of solutions is well known:

Thermal stage Indicative capacity Power implication
Forced air up to ~0.5–1 kW/package Sufficient for classic SoCs; exhausted for AI.
Direct-to-chip liquid (D2C) ~1–3 kW/package Emerging standard in AI racks.
Immersion / advanced cold plate several kW Rack density >100 kW.
Embedded microfluidics (in-stack) experimental Cooling the inner layers of the 3D stack.
Critical coupling: copper versus coolant. In a 3D stack, the power delivery network (copper, vias, planes) and the cooling channels compete for the same Z-height budget. They cannot be designed separately: every watt saved in distribution losses is one less watt to extract, and every millimeter freed by a denser power architecture is space for cooling. Power and thermals become a single co-design problem.

5 — Derivative IV · Voltage architecture
Bringing high voltage close to the chip: the quadratic lever

Here lies the core of Premium’s argument. Delivered power is P = V · I. For a given power, raising the voltage V proportionally reduces the current I. And since conduction loss is Ploss = I² · R, that loss falls with the square of the current reduction. It is the difference between a linear improvement and a quadratic one.

Relative conduction loss (same power, same conductor)

high~0

100%

6.25%

0.09%

0.02%

12 V
48 V
400 V (HVDC)
800 V (HVDC)
For the same power carried by the same conductor, moving from 12 V to 48 V cuts conduction loss ~16×; stepping up to HVDC classes makes it practically negligible. The penalty then shifts to the conversion stages, which is where high-density power electronics competes.

The delivery chain and the industry’s direction

The design consequence is twofold: raise the distribution voltage and bring the final conversion closer to the load, minimizing the high-current run. The industry is already on this path:

Power delivery spine: voltage steps down and current steps up toward the die

Grid

HVDC ~400–800 V

↑ current

Rack

48 V

↑↑

Board

12 V → core

↑↑↑

PoL

<1 V

hundreds of A

Die

Goal: keep high voltage for as long a run as possible and convert to low voltage / high current only in the last millimeter.

  • Rack/row level → HVDC. The industry is migrating to DC distribution in the 400–800 V class to feed AI racks from hundreds of kW to megawatts, reducing copper, losses and the number of conversions.
  • Bus level → 48 V. The de facto standard of the modern data center (including the 48 V busbar of OCP’s Open Rack) versus legacy 12 V: same power, 1/4 of the current, ~1/16 of the loss.
  • Package level → PoL and vertical delivery. Final conversion from 48 V to core voltage (<1 V) integrated under or next to the die, and even backside power delivery, so that the very high current travels minimal distances.

Wide-bandgap (GaN and SiC) is the enabler: it allows faster, denser and more efficient converters that make this near-load conversion viable. It is exactly the terrain where Premium adds value.

6 — Infrastructure and cost
Why voltage is also a capex and opex decision

Raising the distribution voltage does not just save energy: it makes the infrastructure cheaper. The chain of effects is direct:

Lever Effect on consumption (opex) Effect on infrastructure (capex)
↑ Distribution voltage I²R loss falls with the square of the current. Thinner, cheaper conductors and busbars; less copper.
↓ Conversion stages Every conversion avoided removes its loss. Fewer conversion units, less space, fewer points of failure.
Conversion close to the load The high-current run is shortened to the minimum. Simpler PDN on the board; better use of the rack.
Fewer losses → less heat Cooling overhead drops (better PUE). Lower installed cooling capacity per useful kW.

The result is a virtuous circle: fewer losses mean less heat, which means less cooling, which means less energy and less infrastructure for the same useful power delivered to the silicon. In the era of temporal scaling — where silicon densifies without getting cheaper per node — system-level savings shift decisively to the power architecture.

7 — Premium’s positioning
Where Premium fits in this scenario

Huawei’s move illustrates a truth that applies to the whole industry, not just China: as performance densifies in volume, the advantage shifts to whoever can power and cool that volume. Premium operates precisely in that layer, and with criteria — minimum cost, open hardware/software, no vendor lock-in, performance — that fit a market looking for alternatives to both technical and geopolitical lock-in.

Lines of opportunity:

  • High-voltage to point-of-load conversion with wide-bandgap (GaN/SiC) for data center and AI: rack HVDC → 48 V → core, with the final conversion as close as possible to the die.
  • Power architectures for high-density racks aligned with OCP (48 V busbar, evolution toward HVDC), leveraging the open-hardware mandate against closed solutions.
  • Power–thermal co-design: modules where energy delivery and heat extraction are designed together, not separately — the true technical differentiator of the 3D era.
  • Vendor independence at system scale: a neutral power and thermal layer works equally under Western silicon (TSMC/Apple/NVIDIA) or the Chinese path (Huawei/Ascend), covering the ecosystem’s bifurcation.

The useful paradox: sanctions pushed Huawei down a path that increases the world’s dependence on good power delivery and cooling. That demand is agnostic as to who makes the chip — and that is precisely the neutral, open space where Premium can compete.

8 — Conclusion
The lithographer hands the baton to the power engineer

The Tau Law is neither a new law of physics nor the end of Moore; it is constraint-driven innovation. But its value for Premium is independent of whether it succeeds as a standard: any path that stacks more compute into less volume — from East or West — concentrates power and heat, and moves the performance and cost limit to the energy delivery and heat dissipation layer.

Keeping high voltage for as long a run as possible, converting close to the load with wide-bandgap technology, and co-designing power and thermals as a single problem is engineering’s answer to the era of temporal scaling. The verdict on Huawei will come with the Kirin teardowns this autumn; Premium’s is decided by how it capitalizes on a frontier that is shifting, unmistakably, into its domain.

§ Sources

  1. Huawei, official press release: “HUAWEI Presents the Tau (τ) Scaling Law” (ISCAS 2026, Shanghai, May 25, 2026).
  2. CGTN: “From geometry to time: Decoding Huawei’s Tau (τ) Scaling Law” and note on the 1.4 nm-equivalent density target for 2031.
  3. 36Kr (analysis): balanced assessment of the Tau Law and the redefinition of “mature process” as “high-performance process”.
  4. TechWire Asia: Ascend / DeepSeek V4 context and demand for domestic AI silicon.
  5. Canal TI: “Huawei busca reescribir las reglas de los procesadores” (June 8, 2026) — source article.
  6. Power engineering fundamentals (P = V·I; I²R loss; P ≈ α·C·V²·f) and distribution architecture trends (OCP Open Rack 48 V; industry migration to 400–800 V-class HVDC) — domain technical knowledge.

The LogicFolding figures (+53.5% density, +40% efficiency, +12.7% frequency, 1.4 nm-equivalent target by 2031) are Huawei’s claims pending independent validation. The voltage-loss illustrations are normalized calculations for explanatory purposes, not product specifications.

 

Premium PSU
PREMIUM S.A. · Power conversion systems · Barcelona
Technical White Paper PRM-WP-2026-014 · v1.0 · June 2026
Strategic analysis document. premiumpsu.com

Born in Barcelona, Powering the World

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Maintain maximum efficiency and safety of your electronic systems in defense without compromising your equipment
,

Maintain maximum efficiency and safety of your electronic systems in defense without compromising your equipment

Installing high-power electronic products in sealed enclosures presents unique challenges in terms of thermal management. This article discusses how premium power conversion products, such as the TDS-3300 and TDX-3300, can be mounted in sealed enclosures using an optimized approach for heat dissipation. The importance of sealed enclosures is highlighted, along with the use of heat sinks and thermal pads, and precise methods for calculating heat sink size and thermal resistance.

 

In industrial applications, sealed enclosures are essential to protect electronic systems from environmental factors such as moisture, dust, and contaminants. However, these enclosures also pose a significant challenge: effective heat dissipation. High-power conversion products like the TDS-3300, TDX-3300, ODS-3000, and ODX-3000 generate substantial amounts of heat, which, if not properly managed, can compromise performance and reduce the product’s lifespan.

 

Maintain maximum efficiency and safety of your electronic systems in defense without compromising your equipment

This article focuses on how to efficiently manage heat in sealed enclosures using heat sinks and thermal pads. Proper thermal planning is key to ensuring that the equipment operates within a safe temperature range without sacrificing the integrity of the sealed enclosure.

Importance of Sealed Enclosures

Sealed enclosures not only protect electronic components from external elements but also allow their use in harsh environments such as factories, outdoor settings, or marine applications. However, this isolation creates a challenge: heat buildup in a confined space. Without adequate airflow, products like the TDS-3300 and TDX-3300, originally designed to be cooled by internal fans, can overheat.

Thermal management within these enclosures is critical to avoid system failures. A well-designed enclosure, along with the installation of heat sinks, ensures that the generated heat is efficiently evacuated without compromising the enclosure’s seal.

Enclosure Dimensions and Design

It is crucial that the sealed enclosure is large enough to allow proper air circulation around the device. It has been determined that a minimum space of 50 mm on each side of the product allows hot air to disperse evenly, minimizing heat buildup in critical areas.

The design of sealed enclosures must consider not only protection from external agents but also how to manage the heat generated internally. This is where heat sinks play a key role, channeling heat outside the enclosure while maintaining its airtight integrity.

Thermal Coupling with the Heat Sink

One of the most critical factors in thermal management is proper coupling between the heat sink and the product. To ensure efficient heat transfer, it is recommended to use 1 mm thick thermal pads placed strategically on the hottest surfaces of the device. These pads allow the heat sink to conduct heat out of the enclosure without requiring active airflow inside, maintaining the sealed enclosure.

Positioning of Thermal Pads

For products like the TDS-3300 or TDX-3300, thermal pads, such as the Bergquist GPVOUS-0.04-01 or equivalents, approximately 100 x 100 x 1 mm, should be placed where the internal heat sinks are closest to the outer casing. This coupling ensures efficient heat conduction from the inside to the outside of the system, where the heat sink can dissipate the heat.

 

 

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