The 800 V sidecar solves the problem of power distribution to the compute rack. But it does not solve the problem of the power transients that AI silicon workloads generate on millisecond timescales. That window — between 1 and 50 ms — is the territory of the Lithium Ion Capacitor (LIC) and the Battery Backup Unit (BBU), and it is also territory where the discipline of industrial power electronics has a direct and immediate application.

The 1–50 ms window: why it matters

Artificial intelligence workloads generate power transients that did not exist in the previous generation of data centres. When a GPU cluster initiates an intensive compute phase — the first token of an inference, the start of a training step — power demand can ramp in milliseconds from an idle value to the rack’s maximum power. That power step has two consequences.

The first is electrical: the facility rectifier and distribution system cannot respond fast enough. The bus voltage momentarily drops until the supply chain stabilises. If that voltage drop exceeds the silicon’s tolerance threshold — typically ±5% of nominal — the GPU controller activates the throttling mechanism, reducing clock frequency until the voltage recovers. The result is a direct degradation of compute performance.

The second consequence is mechanical and reliability-related: repeated load step and unload cycles accelerate ageing of decoupling capacitors, power modules and rack converters. In racks of 125–140 kW such as NVIDIA’s NVL72, the energy involved in those transients is sufficient to damage components dimensioned for steady-state operation if it is not actively managed.

The SCMI management framework: power capping and PID loop

The OCP EMEA Summit 2026, held in Barcelona in April 2026, added a new dimension to the transient problem: coordinated management from the Data Centre Manager (DCM) level. A joint session by Oracle, AMI and Arm presented Arm SCMI (System Control and Management Interface) as the standard protocol for the DCM to impose power policies at the silicon and power converter level.

The POWERCAP_CAP_SET and POWERCAP_CAP_GET power capping commands allow the DCM to set a consumption ceiling per power domain. Levels CPL0 to CPL3 define four degrees of restriction, from the sustained level (CPL0) to the critical level (CPL3). Concurrent Power Capping (CPC) enables simultaneous restrictions across multiple domains.

The interaction with the closed thermal loop is equally relevant. Without a closed loop coordinating cooling with silicon power demand, the only response to a thermal transient is processor throttling — a performance degradation. With the DCM’s PID loop acting on pumps, valves and CDU flow rate, the system can increase cooling before the silicon reaches its thermal limit, preserving compute performance.

LIC and BBU: the state of the art at rack scale

The reference solution for transient management in the AI rack is a two-stage temporal architecture. The Lithium Ion Capacitor (LIC) covers the ultra-short window of 1 to 50 ms — the energy needed to hold the rack bus while the supply chain responds to the load step. The Battery Backup Unit (BBU) covers the seconds-to-minutes window — the backup needed for an orderly shutdown or to ride through micro-outages.

The LIC is neither a supercapacitor nor a lithium-ion battery. It is a hybrid technology that combines the high specific power of the supercapacitor with an energy density intermediate between the supercapacitor and the battery. In the rack context, a LIC module at rack scale typically provides between 100 and 500 Wh of usable energy with a discharge power of 10–50 kW for the 1–50 ms window, in a format compatible with standard rack U-space. The cycle life of a LIC — typically above 100,000 cycles at 80% depth of discharge — is compatible with the daily cycle count of an AI rack in production.

Implications for the sidecar power converter

For the sidecar converter, the two-stage LIC + BBU architecture implies specific design requirements. The 800 V DC bus must support the connection of LIC and BBU modules without intermediate conversion — which requires that bus voltage tolerance and protection coordination are designed for bidirectional energy flows. The converter supervisor must expose telemetry at the granularity and latency the DCM’s PID loop needs: instantaneous output power, semiconductor temperature, transformer temperature and instantaneous efficiency, updated at intervals below 100 ms.

The converter must also respond to SCMI POWERCAP_CAP_SET/GET commands in times consistent with the control loop dynamics. This is a firmware requirement that today is not standardised in most industrial converters, and one that converter manufacturers will need to address.

Lessons from railway power electronics

The transient management problem in the AI rack is structurally similar to two problems Premium SA has addressed in the railway environment: the management of regenerative braking transients in traction auxiliaries, and the management of load disconnection transients in EN 50155-certified on-board systems. In both cases, the critical window is in the range of tens of milliseconds, the energy involved is in the range of hundreds of watt-hours at power levels of tens of kilowatts, and the reliability requirement is above 99.9% availability over a lifetime of ten to twenty years.

The engineering approach applied to railway traction — conservative derating, accelerated thermal cycling qualification, FMEA at component level — is the same approach that the 1–50 ms transient management problem in the AI rack demands.