The constraint that shifts the frontier toward power

At ISCAS 2026 in Shanghai, Huawei proposed replacing the geometric scaling of Moore’s Law with temporal scaling: optimizing the time it takes a signal to propagate across the chip (the τ constant) rather than the size of the transistor. Its LogicFolding architecture aims to gain density and performance through 3D integration and shorter critical paths, on mature nodes that China can actually fabricate.

For Premium, what matters is not the dispute over whether τ deserves to be called a «law.» It is the inevitable physical consequence of any path that stacks more logic into less volume —be it Huawei’s, TSMC’s, Apple’s or NVIDIA’s—: power density rises, heat concentrates, and the performance ceiling stops being set by the transistor and starts being set by the ability to bring clean energy to the die and to extract the resulting heat.

This document traces that causal chain across four derivatives —energy consumption, performance, heat extraction and voltage architecture— and places Premium’s opportunity at the center of the last three.

What Huawei proposed, and what is real

On 25 May 2026, He Tingbo —president of Huawei’s semiconductor business— presented the Tau (τ) Scaling Law and two supporting technologies: LogicFolding, which folds 2D circuits into vertical 3D stacks to shorten critical-path wiring, and UnifiedBus, a protocol to reduce communication latency at the system level.

The central idea is sound and not new in itself: below ~10 nm, interconnect delay (the wiring’s RC constant) dominates over gate delay. The whole industry is already moving toward system scaling —backside power delivery on the wafer, 3D stacking, hybrid bonding, the CFET roadmap—. What Huawei does is turn that axis into corporate doctrine, because sanctions (no ASML EUV lithography since 2023) close the geometric axis for it.

In other words: Huawei’s path, like those of its rivals, increases the strategic value of advanced power conversion and cooling. The rest of the document develops why.

Two layers of energy: the one that computes and the one lost along the way

A computing system’s consumption splits into two layers with very different dynamics:

Compute layer (on the die)

Dynamic energy roughly follows P ≈ α·C·V²·f. Reducing τ and wiring length lowers the effective capacitance C and allows, for the same frequency, operating at a lower voltage V —and the dependence on V is quadratic—. This is where the +40% efficiency that LogicFolding claims lives. It is a real gain, but bounded to the chip.

Distribution and cooling layer (off the die)

At rack and data-center scale, a growing fraction of the energy never reaches computation: it is lost in voltage conversions, in distribution (I²R losses) and in moving heat (cooling overhead, reflected in the PUE). As AI accelerators scale from hundreds of watts to several kilowatts per package, this second layer dominates total cost of ownership.

The performance ceiling is, increasingly, a power ceiling

Temporal scaling explicitly recognizes that modern performance —and very particularly that of AI— is limited by data movement, not by transistor count. UnifiedBus and LogicFolding attack that «memory wall.» But there is a second wall, physical and less discussed:

• A chip can only switch as fast as it can be fed. Increasingly aggressive current peaks (di/dt) demand a very-low-impedance PDN and point-of-load (PoL) regulators millimeters from the silicon.
• A chip can only sustain its frequency while it can be cooled. Thermal throttling is the most direct way a cooling failure turns into a performance loss.

Thus, the +12.7% in frequency that LogicFolding promises only materializes in the field if power delivery and thermals keep up. Delivered performance is the minimum between what the silicon can do and what the power infrastructure allows it to do.

From a surface problem to a volume problem

3D stacking changes the nature of the thermal problem. In a flat chip, power is dissipated per unit of surface (W/cm²); in a 3D stack it concentrates per unit of volume (W/cm³), and the inner layers sit far from any exchange surface. The progression of solutions is well known:

Bringing high voltage close to the chip: the quadratic lever

Here is the core of Premium’s argument. Delivered power is P = V · I. For a given power, raising the voltage V proportionally reduces the current I. And since conduction loss is P_loss = I² · R, that loss falls with the square of the current reduction. It is the difference between a linear improvement and a quadratic one.

The delivery chain and the sector’s direction

The design consequence is twofold: raise the distribution voltage and bring the final conversion close to the load, minimizing the high-current segment. The industry is already on this path:

• Rack/row level → HVDC. The sector is migrating toward direct-current distribution in the 400–800 V class to feed AI racks of hundreds of kW to megawatts, reducing copper, losses and the number of conversions.
• Bus level → 48 V. The de-facto standard of the modern data center (including OCP’s Open Rack 48 V busbar) versus legacy 12 V: same power, 1/4 of the current, ~1/16 of the loss.
• Package level → PoL and vertical delivery. Final conversion from 48 V to core voltage (<1 V) integrated under or beside the die, and even backside power delivery on the wafer, so that the very high current travels minimal distances.

Wide-bandgap (GaN and SiC) is the enabler: it allows faster, denser and more efficient converters that make this near-load conversion viable. It is exactly the terrain where Premium adds value.

Why voltage is, in addition, a capex and opex decision

Raising the distribution voltage does not only save energy: it cuts infrastructure cost. The chain of effects is direct:

The result is a virtuous circle: fewer losses mean less heat, which means less cooling, which means less energy and less infrastructure for the same useful power delivered to the silicon. In the era of temporal scaling —where silicon densifies without getting cheaper per node— system savings shift decisively to the power architecture.

Where Premium fits in this scenario

Huawei’s move illustrates a truth that applies to the whole sector, not just to China: as performance densifies in volume, the advantage shifts toward whoever knows how to power and cool that volume. Premium operates precisely in that layer, and with criteria —lowest cost, open hardware/software, no vendor lock-in, performance— that fit a market looking for alternatives to lock-in, both technical and geopolitical.

The useful paradox: sanctions pushed Huawei onto a path that increases the world’s dependence on good power delivery and cooling. That demand is agnostic about who makes the chip —and that is precisely the neutral, open space where Premium can compete.

The lithographer hands the baton to the power engineer

The τ Law is neither a new law of physics nor the end of Moore; it is constraint-induced innovation. But its value to Premium is independent of whether it succeeds as a standard: any path that stacks more compute into less volume —from East or West— concentrates power and heat, and shifts the performance and cost ceiling to the energy delivery and dissipation layer.

Keeping high voltage along the longest possible segment, converting close to the load with wide-bandgap technology and co-designing power and thermals as a single problem is the engineering answer to the era of temporal scaling. The verdict on Huawei will come with the Kirin teardowns this autumn; Premium’s is decided by how it capitalizes on a frontier that is moving, unequivocally, into its domain.